Among various semiconductor devices, power devices are required to have a high breakdown voltage and handle a large current while achieving low loss. Although power devices using silicon (Si) semiconductors have conventionally been in common use, attention has in recent years been focused on power devices using compound semiconductors having a wide band gap, such as silicon carbide (SiC). Such compound semiconductor power devices are now being developed. In particular, silicon carbide semiconductors have a dielectric breakdown electric field ten times greater than silicon, and thus can maintain a relatively high reverse breakdown voltage in spite of a narrow depletion layer of a pn junction or a Schottky junction. Hence, silicon carbide semiconductors are expected to be materials for power devices having a low on-state resistance, a high breakdown voltage and low loss. This is because they can be used to reduce the thickness of the semiconductor layer and enhance the doping concentration.
FIG. 15 is a cross sectional view showing a double-implanted, accumulation-mode MISFET (ACCUFET) using SiC, which is suggested by the present inventors in Document 1 (see Osamu Kusumoto and the other 6 persons, “SiC Vertical DACFET”, Materials Science Forum, No. 389-393, pp. 1211-1214).
As shown in this figure, the known accumulation-mode MISFET comprises a low-resistance SiC substrate 1001, a high-resistance SiC layer 1002 that is epitaxially grown on the SiC substrate 1001 and has a higher resistance than the SiC substrate 1001, a p-well region 1003 formed by selectively implanting ions into the surface region of the high-resistance SiC layer 1002, an accumulation channel layer 1004 formed on the surface region of the p-well region 1003 and including a multiple δ-doped layer formed by alternately stacking many δ-doped layers and undoped layers, and a source region 1006 formed by implanting ions into a part of the accumulation channel layer 1004 and containing an n-type impurity at a high concentration. A gate insulating film 1008 is formed over the accumulation channel layer 1004 and a part of the source region 1006, and a gate electrode 1010 is formed on the gate insulating film 1008. A part of the source region 1006 is removed to form a recess, and the well region 1003 is partly exposed at the bottom of the recess. A contact layer 1005 containing a p-type impurity at a high concentration is formed on the bottom of the recess, and a source electrode 1011 is provided on the contact layer 1005 to fill the recess and extend to the top of the source region 1006. The source electrode 1011 makes an ohmic contact with the source region 1006 and the contact layer 1005 by heat treatment. Furthermore, a drain electrode 1012 is formed on the back surface of the SiC substrate 1001 to make an ohmic contact with the SiC substrate 1001.
In this case, the n-type dopant concentration in the high-resistance SiC layer 1002 is usually about 1×1015 cm−3 through 3×1016 cm−3. This dopant concentration depends on a desired breakdown voltage. That is, this dopant concentration becomes lower with the increase of the desired breakdown voltage.
When the accumulation channel layer 1004 has a certain level of high impurity concentration, the channel resistance becomes low. However, in this case, the breakdown voltage decreases. The reason for this is that a depletion layer at the surface of the high-resistance SiC layer 1002 does not extend. That is, there is a trade-off relationship between high breakdown voltage and low loss. Therefore, the impurity concentration in the accumulation channel layer cannot be high.
According to Document 2 (Toshiyuki Ohno, “Recent Progress in SiC-Based Device Processing”, IEICE Transactions, (the Institute of Electronics, Information and Communication Engineers, Vol. J81-C-II, No. 1, pp. 128-133, January, 1998)), nickel is often used for an ohmic electrode of an n-type silicon carbide semiconductor, and the nickel ohmic electrode is subjected to annealing at 900° C. or higher in an atmosphere of an inert gas, such as argon or nitrogen. As a result, nickel silicide (Ni2Si) is formed to contribute to a reduced contact resistance. However, the document says that since the contact resistance of the ohmic electrode varies greatly depending on the doping concentration of silicon carbide, it is difficult to obtain an ohmic electrode at a doping concentration of 1017 cm−3 or less. Therefore, an n-type source region having n-type impurities at a concentration of approximately 1×1019 cm−3 is formed.
On the other hand, the source electrode 1011 needs to directly contact the contact layer 1005, because the contact layer 1005, which is a heavily-doped p-type layer, applies a bias to the well region 1003. To cope with this, a recess is formed in the source region 1006 and the source electrode 1011 is formed along the wall surface of the recess. As a result, a voltage is directly applied from the source electrode 1011 to the contact layer 1005.
However, the structure of the known semiconductor device has the following problems.
Silicon carbide has a large binding energy between carbon and silicon. This makes it difficult to clear crystal defects formed therein due to ion implantation. In particular, when ions are implanted at a high concentration of approximately 1×1019 cm−3 as in the source region, the dose of ions is also large. In this case, defects may cause troubles. Therefore, ions need to be implanted with the substrate kept at a high temperature of 500° C. or higher, and the temperature of activation annealing after the implantation needs to be set at a high temperature of 1400° C. or higher. In turn, the fabrication process is complicated, resulting in increased cost.
In order to recover crystallinity further perfectly, the annealing temperature needs to be high. However, when annealing is conducted at 1500° C. or higher, silicon is selectively evaporated from the surface of SiC to form pits or cause step bunching, and flatness of the surface is degraded.